DocumentCode
2349497
Title
Pre-silicon 22/20 nm compact MOSFET models for bulk vs. FD SOI low-power circuit benchmarks
Author
Bol, David ; Bernard, Sébastien ; Flandre, Denis
Author_Institution
ICTEAM Inst., Univ. Catholique de Louvain, Louvain-la-Neuve, Belgium
fYear
2011
fDate
3-6 Oct. 2011
Firstpage
1
Lastpage
2
Abstract
The pre-silicon 22/20nm LSTP models we generated are available on-line and can be used for fair bulk vs. FD SOI benchmarks. The proposed modeling methodology unified for bulk and FD SOI can further be used to generate models for LOP process flavor and/or 16nm CMOS node.
Keywords
CMOS integrated circuits; MOSFET; elemental semiconductors; low-power electronics; semiconductor device models; silicon; silicon-on-insulator; CMOS node; FD SOI low-power circuit benchmarks; LOP process; LSTP models; Si; pre-silicon compact MOSFET models; size 16 nm; size 20 nm; size 22 nm; Benchmark testing; CMOS integrated circuits; Delay; Integrated circuit modeling; MOSFET circuits; Random access memory; Semiconductor device modeling;
fLanguage
English
Publisher
ieee
Conference_Titel
SOI Conference (SOI), 2011 IEEE International
Conference_Location
Tempe, AZ
ISSN
1078-621X
Print_ISBN
978-1-61284-761-0
Electronic_ISBN
1078-621X
Type
conf
DOI
10.1109/SOI.2011.6081697
Filename
6081697
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