CREMA: Fusing Memory and Processing for Parallel Raytracing

Under certain conditions, accelerator data structures significantly reduce a raytracer´s runtime. But for most of them, unfortunately, the literature does not provide any a priori indication of whether or not they yield any speedup at all in a particular scene. For others though, the literature does provide lower bounds, but those accelerators are of rather theoretical utility. A straight forward analysis indicates that both the sequential processing and memory accesses constitute an inherent bottleneck for any of the software-centered raytracers. By contrast, this paper proposes a parallel hardware architecture, which renders a scene in constant time O(1) per ray, regardless of the scene´s size and complexity. A prototypical implementation on a field-programmable gate array validates the architecture´s feasibility and provides first laboratory results.