From C4 to micro-bump: Adapting lead free solder electroplating processes to next-gen advanced packaging applications

SnAg solder is the industry standard for lead-free wafer bumping. SnAg electroplating chemistry for C4 bumping must be capable of achieving tight performance standards over a wide range of applications: mushroom or in-via electroplating, a diverse range of die designs and pattern densities, and over a wide range of plating rates, including high speeds to enable higher throughput. Beyond C4 applications, SnAg electroplating chemistries must also deliver strong performance on emerging micro-bumping and Cu pillar capping applications, leading to new materials challenges and new demands on both the solder and copper electroplating chemistries. Electrodeposited SnAg solder and Cu pillar performance is controlled by the specially formulated additives used during the electroplating process, paired with optimized high purity, low-alpha emitting inorganic metal salts and acids. Selection of robust, versatile SnAg and Cu plating chemistries capable of operation at high plating rate is critical to achieving optimized high volume, high throughput, and cost effective manufacturing. Improper additive selection can lead to a number of defects, which can manifest after plating, after reflow, or during reliability testing. These defects include as-plated defected or rough surface morphology, post-reflow macro-voiding, micro-voiding, bridging, and Ag₃Sn plate formation, and poor height uniformity control across the die and wafer. These defects can lead to critical failures that lower yield and require wafer rework or wafer scrapping. To reduce the frequency of solder bumping, micro-bumping and Cu pillar capping defectivity, solder and Cu electroplating processes must be selected to enable wide process versatility and stability. In this paper, a wide range of bumping defects is introduced, root causes are discussed, and defect mitigation strategies are presented. Further, next-generation SnAg electroplating chemistries are presented that are designed to minimize solder def- ctivity and provide high performance, high yield, wide process windows, and high throughput options over a wide range of applications.