DocumentCode
2349887
Title
Statistical design and optimization of SRAM cell for yield enhancement
Author
Mukhopadhyay, Saibal ; Mahmoodi, Hamid ; Roy, Kaushik
Author_Institution
Dept. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
fYear
2004
fDate
7-11 Nov. 2004
Firstpage
10
Lastpage
13
Abstract
We have analyzed and modeled the failure probabilities of SRAM cells due to process parameter variations. A method to predict the yield of a memory chip based on the cell failure probability is proposed. The developed method is used in an early stage of a design cycle to minimize memory failure probability by statistically sizing of SRAM cell.
Keywords
SRAM chips; failure analysis; integrated circuit yield; probability; statistical analysis; SRAM cell optimization; cell failure probability; memory chip; memory failure probability; process parameter variations; statistical design; yield enhancement; Circuit faults; Design optimization; Doping profiles; Fluctuations; MOSFETs; Probability; Random access memory; Resource description framework; Semiconductor process modeling; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on
ISSN
1092-3152
Print_ISBN
0-7803-8702-3
Type
conf
DOI
10.1109/ICCAD.2004.1382534
Filename
1382534
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