Benchmarking and hardware implementation of JPEG-LS

Author

Savakis, Andreas ; Piorun, Michael

Author_Institution

Dept. of Comput. Eng., Rochester Inst. of Technol., USA

Volume

2

fYear

2002

fDate

2002

Abstract

The JPEG-LS algorithm is one of the recently designated standards for lossless compression of grayscale and color images. Simulation results for lossless and near lossless compression of various image types are presented in order to explore the algorithm´s effectiveness for a number of applications. A hardware implementation using VHDL is proposed and the schematic of a JPEG-LS codec, that is capable of standard-compliant lossless and near lossless encoding and decoding, has been generated using the Synopsys synthesis tool. Hardware implementation of the proposed solution on an FPGA allows for real-time processing of large image volumes.

Keywords

data compression; decoding; hardware description languages; image coding; image colour analysis; logic design; performance evaluation; FPGA; JPEG-LS codec; Synopsys synthesis tool; VHDL; benchmarking; color images; decoding; grayscale images; lossless compression; lossless encoding; Algorithm design and analysis; Codecs; Context modeling; Decoding; Encoding; Field programmable gate arrays; Gray-scale; Hardware; Image coding; Image edge detection;

fLanguage

English

Publisher

ieee

Conference_Titel

Image Processing. 2002. Proceedings. 2002 International Conference on

ISSN

1522-4880

Print_ISBN

0-7803-7622-6

Type

conf

DOI

10.1109/ICIP.2002.1040109

Filename

1040109