• DocumentCode
    2350178
  • Title

    A comparative analysis of fuzzy ART neural network implementations: the advantages of reconfigurable computing

  • Author

    Poire, Pascal ; Cantin, Marc-Andre ; Daniel, Herve ; Blaquiere, Yves ; Savaria, Yvon

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Ecole Polytech. de Montreal, Que., Canada
  • fYear
    1998
  • fDate
    15-17 Apr 1998
  • Firstpage
    304
  • Lastpage
    305
  • Abstract
    The paper analyzes the performance differences found between software and hardware/sofware implementations of a reformulated fuzzy ART neural network algorithm. This reformulated algorithm is a solution for a real time radar signal clustering problem. The software implementations run on a 50 MHz TMS320C40 DSP, and the hardware/sofware implementation runs on the same DSP for its software part, whereas the FPGA based application specific hardware accelerator is realized on MiroTech´s X-CIM TIM40 module. This investigation of FPGA based acceleration gave excellent results for our application: acceleration factors up to 68.9 have been reached
  • Keywords
    ART neural nets; digital signal processing chips; field programmable gate arrays; fuzzy neural nets; neural chips; radar signal processing; reconfigurable architectures; FPGA based acceleration; FPGA based application specific hardware accelerator; MiroTech; TMS320C40 DSP; X-CIM TIM40 module; acceleration factors; comparative analysis; fuzzy ART neural network implementations; real time radar signal clustering problem; reconfigurable computing; reformulated fuzzy ART neural network algorithm; software implementations; Acceleration; Application software; Clustering algorithms; Digital signal processing; Field programmable gate arrays; Fuzzy neural networks; Hardware; Neural networks; Performance analysis; Subspace constraints;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on
  • Conference_Location
    Napa Valley, CA
  • Print_ISBN
    0-8186-8900-5
  • Type

    conf

  • DOI
    10.1109/FPGA.1998.707927
  • Filename
    707927