Title :
Probabilistic identification of critical components for circuit delays
Author :
Wessels, David ; Muzio, Jon C.
Author_Institution :
VLSI Design & Test Group, Victoria Univ., BC, Canada
Abstract :
It is clear that defect fault tolerance must eventually be expanded to include tolerance of delay-inducing defects. A circuit operating near its optimal speed is particularly sensitive to delay increases caused by defects in components which lie on maximum length or near-maximum length true paths. For circuits with many long false paths the identification of key paths, and therefore key components, is a difficult problem. The authors use a randomized algorithm to quickly identify a circuit´s optimal operating speed, and also the components in which delay defects are most likely to adversely affect circuit operation. Categorization of these components permits an optimal use of available resources in the introduction of delay defect tolerance
Keywords :
fault diagnosis; benchmark analysis; circuit delays; critical components; critical path analysis; defect fault tolerance; delay-inducing defects; identification of key paths; optimal speed; probability; randomized algorithm; Circuit faults; Circuit testing; Clocks; Delay; Fault tolerance; Inverters; Logic design; Pulse circuits; Timing; Very large scale integration;
Conference_Titel :
Defect and Fault Tolerance in VLSI Systems, 1993., The IEEE International Workshop on
Conference_Location :
Venice
Print_ISBN :
0-8186-3502-9
DOI :
10.1109/DFTVS.1993.595801