Investigation of a TSV-RDL in-line fault-diagnosis system and test methodology for wafer-level commercial production

In the first three quarters of 2013, semiconductor industry witnessed a great multiplication of 12-inch TSV wafers mounting to 1 million plus scale. Despite this increasing popularity, TSV technology suffers from high cost due to yield loss caused by process defects. Poor insulation and connectivity are the major problems for TSV and RDL(Re-Distribution Line) structures. Without a cost-effective test system and methodology, the faulty TSVs may be stacked onto good ones and therefore bring forth an increasing chip cost. In this paper, the leakage current and pathway resistance are characterized for TSV and RDL structures, and a two-step in-line test methodology was proposed to pinpoint these defects and screen out KGDs (Known Good Dies) on the wafer. Also, a wafer-level fault-diagnosis system based on the proposed technology was built, including a probe station, an analyzer and a controller software, and two test instances were carried out on the test system. The test results demonstrated the capability of the test methodology and system, and proved the potential feasibility of the methodology for volume pre-bond test.