Title :
Bonding technologies for chip level and wafer level 3D integration
Author :
Sakuma, Keita ; Skordas, Spyridon ; Zitz, Jeffrey ; Perfecto, Eric ; Guthrie, William ; Guerin, Luc ; Langlois, Richard ; Liu, Hongying ; Ramachandran, Kishore ; Lin, Weisi ; Winstel, Kevin ; Kohara, S. ; Sueoka, Kazuhisa ; Angyal, Matthew ; Graves-Abe, T
Author_Institution :
Semicond. R&D Center, IBM, Hopewell Junction, VA, USA
Abstract :
This paper provides a comparison of bonding process technologies for chip and wafer level 3D integration (3Di). We discuss bonding methods and comparison of the reflow furnace, thermo-compression, Cavity ALignment Method (CALM) for chip level bonding, and oxide bonding for 300 mm wafer level 3Di. For chip 3Di, challenges related to maintaining thin die and laminate co-planarity were overcome. Stacking of large thin Si die with 22 nm CMOS devices was achieved. The size of the die was more than 600 mm2. Also, 300 mm 3Di wafer stacking with 45 nm CMOS devices was demonstrated. Wafers thinned to 10 μm with Cu through-silicon-via (TSV) interconnections were formed after bonding to another device wafer. In either chip or wafer level 3Di, testing results show no loss of integrity due to the bonding technologies.
Keywords :
CMOS integrated circuits; copper; integrated circuit interconnections; silicon; three-dimensional integrated circuits; wafer bonding; 3Di wafer stacking; CALM; CMOS devices; Cu; Si; TSV interconnections; cavity alignment method; chip bonding process technologies; chip level bonding; oxide bonding; reflow furnace; size 10 mum; size 22 nm; size 300 mm; size 45 nm; thermo-compression; thin silicon die; through-silicon-via interconnections; wafer level 3D integration; Bonding; CMOS integrated circuits; Cavity resonators; Laminates; Stacking; Three-dimensional displays; Through-silicon vias;
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th
Conference_Location :
Orlando, FL
DOI :
10.1109/ECTC.2014.6897355
