Design of highly parallel residue arithmetic circuits based on multiple-valued bidirectional current-mode MOS technology

Author

Kameyama, Michitaka ; Sekibe, Tsutomu ; Higuchi, Tatsuo

Author_Institution

Dept. of Electron. Eng., Tohoku Univ., Sendai, Japan

fYear

1988

fDate

0-0 1988

Firstpage

6

Lastpage

13

Abstract

A residue arithmetic circuit based on multiple-valued bidirectional current-mode MOS technology is proposed. Each residue digit is represented by multiple-valued coding suitable for highly parallel computation. Using the coding, mod m/sub i/ multiplication can be simply performed by a shift operation. In mod m/sub i/ addition, radix-five signed-digit full adders are used to obtain a high degree of parallelism and multiple-operand addition, so that the high-speed arithmetic operation can be achieved. A novel parallel scaling algorithm is discussed. A mod-seven three-operand multiply-adder is designed for an integrated circuit based on 10- mu m CMOS technology.<>

Keywords

CMOS integrated circuits; digital arithmetic; digital integrated circuits; logic design; many-valued logics; CMOS technology; highly parallel residue arithmetic circuits; integrated circuit; multiple-operand addition; multiple-valued bidirectional current-mode MOS technology; multiple-valued coding; parallel scaling algorithm; radix-five signed-digit full adders; Arithmetic; Circuits; Large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Multiple-Valued Logic, 1988., Proceedings of the Eighteenth International Symposium on

Conference_Location

Palma de Mallorca, Spain

Print_ISBN

0-8186-0859-5

Type

conf

DOI

10.1109/ISMVL.1988.5142

Filename

5142