• DocumentCode
    2351145
  • Title

    FDSOI design portability from BULK at 20nm node

  • Author

    Pelloie, Jean-Luc

  • Author_Institution
    SOI Technol., ARM Grenoble, Grenoble, France
  • fYear
    2011
  • fDate
    3-6 Oct. 2011
  • Firstpage
    1
  • Lastpage
    29
  • Abstract
    A standard BULK ASIC design flow can be used for FDSOI, an existing BULK logic design can be directly ported to FDSOI and expected to bring tremendous advantage like: low-voltage high-performance, in low voltage SRAM undoped channel brings higher margins and better RF features if you combine high-resistivity substrate are discussed. FDSOI process on SOI wafer are also discussed.
  • Keywords
    SRAM chips; application specific integrated circuits; logic design; silicon-on-insulator; BULK ASIC design flow; BULK logic design; FDSOI design portability; RF feature; SOI wafer; Si; low voltage SRAM; size 20 nm; Application specific integrated circuits; Batteries; History; IP networks; Industries; Production; Silicon on insulator technology;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference (SOI), 2011 IEEE International
  • Conference_Location
    Tempe, AZ
  • ISSN
    1078-621X
  • Print_ISBN
    978-1-61284-761-0
  • Electronic_ISBN
    1078-621X
  • Type

    conf

  • DOI
    10.1109/SOI.2011.6081796
  • Filename
    6081796
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2351145