Hierarchically Heterogeneous Network-on-Chip

We observed several inefficiencies arising from the utilization of a global network to interconnect local bus clusters in our previous work. The observations were made with applications running on an FPGA prototype of a multimedia processing platform. The presented network-on-chip concept has been designed to eliminate these inefficiencies. This hierarchically heterogeneous architecture provides increased bandwidth inside processing clusters by local switches that replace shared buses. Features include priority-based low-latency arbitration logic with a memory space conserving programming model. Run-time reconfigurable source routing generates output port selects for the traversed path. The realization was carefully designed for easy and efficient implementation on any technology. Arbitrated 5 times 5 mesh switch implementations on an ASIC technology feature as few as two thousand gates and only five levels of logic on the critical path.