DocumentCode :
2351208
Title :
Influence of fin height on poly-Si/PVD-TiN stacked gate FinFET performance
Author :
Hayashida, T. ; Endo, K. ; Liu, Y.X. ; Uchi, S.O. ; Matsukawa, T. ; Mizubayashi, W. ; Migita, S. ; Morita, Y. ; Ota, H. ; Hashiguchi, H. ; Kosemura, D. ; Kamei, T. ; Tsukada, J. ; Ishikawa, Y. ; Yamauchi, H. ; Ogura, A. ; Masahara, M.
Author_Institution :
Sch. of Sci. & Technol., Meiji Univ., Kawasaki, Japan
fYear :
2011
fDate :
3-6 Oct. 2011
Firstpage :
1
Lastpage :
2
Abstract :
In this paper the device performance of n+ poly-Si/PVD-TiN stacked gate FinFETs with different Hfin´s is experimentally investigated. It was found that mobility enhances in the tall Hfin devices due to the increased tensile stress. However, as Lg decreases, Ion for tall Hfin case becomes worse, probably due to high Rsp. It was also confirmed that Vth variation increases with increasing Hfin due to the rough etcing of fin sidewall.
Keywords :
MOSFET; carrier mobility; elemental semiconductors; etching; silicon; silicon-on-insulator; titanium compounds; Si-TiN; fin height influence; mobility enhancement; n+ poly-Si-PVD-TiN stacked gate FinFET; rough etching; tall Hfin device; tensile stress; FinFETs; Junctions; Logic gates; Materials; Resistance; Stress; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
SOI Conference (SOI), 2011 IEEE International
Conference_Location :
Tempe, AZ
ISSN :
1078-621X
Print_ISBN :
978-1-61284-761-0
Electronic_ISBN :
1078-621X
Type :
conf
DOI :
10.1109/SOI.2011.6081800
Filename :
6081800
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=2351208
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