Reduction of fault detection costs through testable design of sequential architectures with signal feedbacks

Testability analysis can be performed through classification of all possible simple interconnection topologies, definition of testability conditions on the function performed by the cells composing the circuit and identification of the composition rules of such interconnections and of the testability conditions determined. This approach works well whenever feedforward architectures are studied. Application of such an approach to irregular architectures with cycles (signal feedbacks) is presented