Title :
Thread mapping using system-level throughput prediction model for shared memory multicores
Author :
Mitra, Rajendu ; Joshi, Bharat S. ; Adams, Ryan S.
Author_Institution :
Dept. of Electr. & Comput. Eng., Univ. of North Carolina at Charlotte, Charlotte, NC, USA
Abstract :
The primary purpose of the current paper is to design a fast and accurate performance model framework for exploring various thread-to-core mapping strategies (MS) and estimating steady state cycles per instruction (CPI). It is directed towards efficiently exploring these performance metrics for large parallel applications for shared memory multicores. This work establishes a hybrid Markov Chain Model (MCM) and Model Tree (MT) based system-level performance prediction model framework. The model is validated with an Electromagnetics application for 12 different mapping strategies. The average performance prediction error is 0.168% with standard deviation of 3.866%. The total run time of model is of the order of minutes, whereas the actual application execution time is in terms of several days.
Keywords :
Markov processes; multi-threading; performance evaluation; shared memory systems; trees (mathematics); electromagnetic application; hybrid Markov chain model; model tree based system-level performance prediction model; parallel applications; performance metrics; performance prediction error; shared memory multicores; steady state cycle per instruction; system-level throughput prediction model; thread-to-core mapping strategies; Computational modeling; Instruction sets; Magnetic cores; Mathematical model; Multicore processing; Predictive models; Steady-state; Machine Learning; Multicore; Performance Evaluation; Performance Modeling; Performance Prediction; Stochastic Analysis; Thread Mapping;
Conference_Titel :
Performance Computing and Communications Conference (IPCCC), 2014 IEEE International
Conference_Location :
Austin, TX
DOI :
10.1109/PCCC.2014.7017045
