• DocumentCode
    2351354
  • Title

    Process and design issues in a 600 V bonded wafer process

  • Author

    Beasom, J.D. ; McLachlan, C.J.

  • Author_Institution
    Harris Corp., Melbourne, FL, USA
  • fYear
    1994
  • fDate
    3-6 Oct 1994
  • Firstpage
    37
  • Lastpage
    38
  • Abstract
    Describes a bipolar process which provides moderate voltage vertical devices and 600V lateral devices. High breakdown is achieved using relatively thin islands with no buried layer. Island thickness and bond oxide thickness are the two material parameters which have a large influence on breakdown when island doping has been optimized. Island thickness in this work was chosen to be greater than 20 microns so that there is enough island under the base of the vertical bipolars to provide a low collector resistance. The maximum thickness used was 40 microns which is about the maximum thickness through which it is practical to RIE etch to form the lateral isolation trenches. The bond and side oxide thicknesses were set at 4 microns to achieve 600V breakdown in the chosen island thickness
  • Keywords
    isolation technology; power bipolar transistors; semiconductor doping; silicon-on-insulator; sputter etching; wafer bonding; 20 to 40 micron; 600 V; RIE; bipolar process; bond oxide thickness; bonded wafer process; collector resistance; island doping; island thickness; lateral devices; lateral isolation trenches; material parameters; side oxide thickness; vertical devices; Breakdown voltage; Doping; Electric breakdown; Plasma measurements; Process design; Protection; Stress; Surface treatment; Wafer bonding; Wet etching;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    SOI Conference, 1994 Proceedings., 1994 IEEE International
  • Conference_Location
    Nantucket, MA
  • Print_ISBN
    0-7803-2406-4
  • Type

    conf

  • DOI
    10.1109/SOI.1994.514223
  • Filename
    514223