Study of TSV thinning wafer strength enhancement for 3DIC package

Interfacial delamination between backside of TSV thin wafer silicon, low temperature PECVD silicon nitride and UBM (under bump metallurgy) layer under room temperature and thermal cycling or processing have been investigated in this paper. FEA (Finite element analysis) was used to assessment the thermal stresses and the driving force of thin wafer bump UBM delamaination. The 3D modeling results were validated by process improve solutions which are including add a dielectric materials PBO (polybenzoxazole) buffer layer to release stresses and adjust UBM metal structure thickness to reduce UBM corner stresses. In the other hand, seeking enhancement of interfacial adhesion between thin wafer silicon and PECVD SiNx is important work in parallel. Integrate PECVD SiNx adhesion enhanced on TSV backside via reveal process and addition PBO buffer layer, reduce UBM metal thickness during C4 bump formation process was effectively to release die stresses (increase die strength around 8 times) for delamination free. Eliminate die crack issue during Back-End stacking process is another good improve process yield achievement. At the same time, Interposer die warpage has 70% improved from crying direction to close to fully flat interposer die which is good achievement for Back-End chip to chip stacking process. The Mid-End process improvement was proved and validated consistent with thermal stress simulation.