Challenges in 3D die stacking

Many semiconductor companies are currently engaged in 3D system integration. The assembly of 3D compliant chips becomes a vital factor of the 3D application success and reliability. Major challenges are provided by very low chip thickness, large die size, small interconnect diameter and pitch. Diverse 3D assembly technologies and methods are currently under investigations which address these specific technical challenges. Stable and volume capable assembly processes must be developed in order to manufacture such products in future with reasonable cost. Wafer-to-wafer (W2W) assembly is not yet recommended for most of the advanced 3D applications since it still suffering from too high yield losses what would translate into unacceptable W2W stack yield. For that reason the die-to-die (D2D) assembly is considered as the more efficient way for the time being. For that reason we´re developing integrated assembly and test concepts on 300 mm wafer size to evaluate and validate various assembly technologies regarding to their capabilities with respect to interconnect materials, dimension, pitch and I/O density.