High performance submicron SOI devices with silicon film thickness below 50 nm

Two different options are available for submicron SOI devices: one is to keep the silicon thickness relatively thick, about 100 nm, in using a complex architecture as for bulk devices; the second one is to reduce the silicon film thickness below 50nm for sub 0.25 μm devices, in order to obtain fully depleted devices. The main problem in this last case can be the dispersion of the electrical parameters due to a silicon thickness nonuniformity. But the benefits are the reduction of short channel effects, a better control of the impact ionization and the improvement of the subthreshold slope that allows lower threshold voltage values. The sensitivity to silicon thickness is not so severe in practice than it can be shown in theoretical simulations, due to a balance between the doping level and the silicon thickness for a constant implant dose, used for channel doping