Investigation of body effect of fully depleted n channel SOI device as a function of body bias

There have been several papers on threshold voltage models for fully depleted SOI NMOS devices. The particular case of the fully depleted SOI MOSFET under negative substrate bias has been discussed previously. However all the discussion so far has dealt with the case of low drain bias (typically 0.1 V). The important case of higher drain bias (a typical bias condition in circuits) has not been studied in detail. In this paper, the characterization result from subhalf-micron fully depleted SOI MOSFETs under such bias conditions is presented, followed by an analysis through device simulation which reveals the device physics that determines threshold behavior under such bias conditions