Underfilling techniques comparison in 3D CtW stacking approach

Die stacking in 3D integration increasingly deals with smaller soldered joints on flip chips which have to meet reliability requirements especially thermal cycling, vibrations, shocks. Adding an underfill between stacked chips is a solution to improve the structural integrity of those joints. In this work, different underfilling techniques are compared in chip to wafer (CtW) approach: one capillary underfill (CUF) and three pre-applied underfills (PAUF) including one non conductive paste (NCP) and two wafer level underfills (WLUF). These underfilling solutions are assessed using a test vehicle including daisy chains for electrical tests. Preconditioning and temperature cycling tests were carried out to monitor reliability. CUF and NCP enable to get good interconnections electrical resistance after 500 cycles. On the other side, WLUF process currently appears to be harder to implement because of lack of reproducibility and polymer entrapment at the bonding interface, preventing a reliable electrical contact. Advantages and drawbacks of each underfilling processes are also discussed regarding for instance maturity, easiness of process, throughput, creeping risks, entrapment risks, fine pitch and fine gap compatibility. It is obvious that PAUF are inevitable for 3D high density involving gap between stacked chips. However, related process speed is still low for PAUF. Further work on products and processes is thus needed to get reliability performances and cost-effectiveness suitable with high volume manufacturing.