Physical modeling of beneficial dynamic floating-body effects in non-fully depleted SOI CMOS circuits

The floating-body configuration is desirable in scaled SOI CMOS technology because of area efficacy. Unfortunately it portends various problems, one of which is the premature parasitic-BJT breakdown that occurs in both fully depleted (FD) and non-fully depleted (NFD) SOI MOSFETs. In the NFD device, other floating-body effects, some of which can be beneficial, are apparent at drain-source voltages below the breakdown because of the sensitivity of threshold voltage to the body-source bias. This bias, which can be forward or reverse in dynamic operation of the MOSFET, is due to positive or negative excess majority-carrier densities in the floating body. In this paper, we present a physical model for the NFD/SOI MOSFET and use it in a circuit simulator (SOISPICE) to identify and assess beneficial floating-body effects in dynamic operation of scaled CMOS digital circuits