DocumentCode
235157
Title
Board level reliability and surface mount assembly of 0.35mm and 0.3mm pitch wafer level packages
Author
Keser, Beth ; Alvarado, Rey ; Choi, Anthony ; Schwarz, Mathias ; Bezuk, Steve
Author_Institution
Qualcomm Technol. Inc., San Diego, CA, USA
fYear
2014
fDate
27-30 May 2014
Firstpage
925
Lastpage
930
Abstract
Board level reliability studies have been performed on wafer level packages (WLP) on various die sizes with 0.35mm and 0.3mm ball pitches. The 0.35mm pitch test vehicles included 4mm × 4mm, 5mm × 5mm, and 6mm × 6mm package sizes. The 0.3mm pitch test vehicles were 3mm × 3mm and 4mm × 4mm. All test vehicles were fully populated ball arrays. The parts were assembled at 2 different suppliers. All of the WLPs studied passed drop shock. All of the test vehicles passed board level temperature cycle initially except for the 6mm × 6mm. The SMT process optimization included variations of stencil aperture ratios. These modifications impacted temperature cycling reliability. The reliability of the largest package size was improved from this optimization.
Keywords
optimisation; reliability; surface mount technology; wafer level packaging; SMT process optimization; board level reliability; board level temperature cycle; pitch wafer level packages; stencil aperture ratios; surface mount assembly; temperature cycling reliability; test vehicles; Assembly; Electric shock; Passivation; Semiconductor device reliability; Temperature measurement; Vehicles;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th
Conference_Location
Orlando, FL
Type
conf
DOI
10.1109/ECTC.2014.6897398
Filename
6897398
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