High level synthesis for designing custom computing hardware

Author

Doncev, Goran ; Leeser, Miriam ; Tarafdar, Shantanu

Author_Institution

Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA, USA

fYear

1998

fDate

15-17 Apr 1998

Firstpage

326

Lastpage

328

Abstract

We apply High Level Synthesis (HLS) to the design of FPGA based computing systems. HLS allows for a level of design space exploration unrealizable with Register Transfer Level (RTL) techniques. The use of HLS tools allow designers to prototype their designs with high quality results and fast turn around times. Our design flow makes use of Synopsys Behavioral Compiler (BC) followed by logic synthesis to map designs onto the Altera RIPP10 board. We illustrate our approach with a case study: the design of a DTMF receiver from a high-level behavioral description down to implementation on the RIPP10 board. We were able to design working hardware, meet our delay constraints and achieve 90% utilization of the available FPGAs. The final design had approximately 90000 gate equivalents

Keywords

field programmable gate arrays; high level synthesis; Altera RIPP10 board; DTMF receiver; FPGA based computing systems; RIPP10 board; Synopsys Behavioral Compiler; custom computing hardware design; delay constraints; design flow; design space exploration; high level synthesis; high-level behavioral description; logic synthesis; Band pass filters; Clocks; Detectors; Field programmable gate arrays; Frequency; Hardware; High level synthesis; Logic design; Logic testing; Routing;

fLanguage

English

Publisher

ieee

Conference_Titel

FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on

Conference_Location

Napa Valley, CA

Print_ISBN

0-8186-8900-5

Type

conf

DOI

10.1109/FPGA.1998.707938

Filename

707938