DocumentCode
2351679
Title
Implementing C algorithms in reconfigurable hardware using C2Verilog
Author
Soderman, Donald ; Panchul, Yuri
Author_Institution
CompiLogic Corp., San Jose, CA, USA
fYear
1998
fDate
15-17 Apr 1998
Firstpage
339
Lastpage
342
Abstract
A new full featured ANSI C to synthesizable RTL Verilog compiler, C2Verilog, was used to implement several system-level algorithms in a variety of IC implementations. This paper discusses the results achieved implementing a compression-decompression, a prime number generation, and a sorting algorithm in reconfigurable hardware
Keywords
circuit layout CAD; field programmable gate arrays; sorting; ANSI C; C algorithms implementation; C2Verilog; IC implementations; compression-decompression; prime number generation; reconfigurable hardware; sorting algorithm; synthesizable RTL Verilog compiler; system-level algorithms; Analytical models; Arithmetic; Clocks; Field programmable gate arrays; Hardware design languages; Logic; Propagation delay; Random access memory; Software algorithms; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
FPGAs for Custom Computing Machines, 1998. Proceedings. IEEE Symposium on
Conference_Location
Napa Valley, CA
Print_ISBN
0-8186-8900-5
Type
conf
DOI
10.1109/FPGA.1998.707944
Filename
707944
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