Development and characterization of new generation panel fan-out (P-FO) packaging technology

Wafer Level Packaging (WLP) is a packaging technology focusing on integrated circuit (IC) packaging at wafer level instead of die level. WLP essentially consists of IC foundry fabrication process and subsequent device interconnection and back-end passivation process. The general wafer level packages (WLPs) are designed for fan-in chip scale packaging but the shrinkage of pad pitch and size at the chip to package interface is much faster than the shrinkage at the package to board interface. The embedded package technologies are developed to provide larger package size in order to offer a sufficient area to accommodate the redistribution interconnection with standard pitches at the packaging. Embedded technology (FO-WLP / eWLB and embedded die) are unique technological breakthroughs enabling further growth of next-generation packaging modules and brings several benefits such as small form factor of packages, electrical and thermal performance improvement and cost reduction for IDMs. Compare to FO-WLP, panel level packaging (PLP) has the advantage of using large panel processing compare with FO-WLP while 12" is commonly used. Hence panel fan-out package (P-FO) has a better cost down potential than FO-WLP. To demonstrate the new generation panel fan-out package conception, the several hetero-technologies are integrated into the packaging which composed of PCB, LCD, Bumping and FOWLP has substantially broadened the spectrum of the well established wafer level packaging (WLP) technologies. The new generation panel fan-out packaging combines the different infrastructures from several fields to realize the conception. The achieved results for the package, such as the large panel size process and precise die alignment capability point to the outstanding potential of this novel hetero-system. In this paper, mixing PCB, semiconductor back-end, semiconductor WLP and LCD Gen 2.5 (370×470mm) size processing technologies combined with innovation as well as integration of - -FO techniques are proposed, including high accuracy die bonding and die shift compensation at film lamination, lower warpage sheet form film lamination, good copper trace plating uniformity control at large panel area and also precise photolithographic technique. In addition to technology elaboration and process depiction, relevant experimental data and final reliability test results on board level have also been thoroughly demonstrated and discussed.