Integrity of gate oxides formed on SIMOX wafers

The integrity of gate oxides formed on the device surfaces of SIMOX wafers has been a concern because of the structural imperfection of SIMOX superficial silicon layers compared to bulk silicon and the potential for metal contamination during the extended oxygen implantation. Although procedures for improving the crystalline perfection of the surface layer have been developed, and steps taken by oxygen implanter modification and introduction of TCA into the anneal ambient to reduce sources of metal contamination, the concern has remained because of the relative newness of the technology and the limited oxide integrity data presented for SIMOX structures so far. In this paper, we present results of ramp voltage breakdown and constant current charge to breakdown measurements on 6 and 20 nm gate oxides formed on SIMOX surfaces prepared by standard cycle SIMOX annealing in ambients containing various halogen levels, and variations in implantation screen oxide presence and thickness. This latter variation was done by processing `standard SIMOX´ material without screen oxide, and forming a tapered screen oxide on a second SIMOX batch by gradual immersion oxide etching. The tapered screen oxide has been found to provide spatially controlled variation in SIMOX dislocation density for correlation with the electrical parameters. Homogeneous bulk silicon wafers were used as controls in all the SIMOX anneal process variations, and un-annealed bulk control wafers were also included. Atomic force microscopy (AFM) was used to measure surface roughness for correlation with the process variables