DocumentCode
2351807
Title
Optimal wire retiming without binary search
Author
Lin, Chuan ; Zhou, Hai
Author_Institution
Electr. & Comput. Eng., Northwestern Univ., Evanston, IL, USA
fYear
2004
fDate
7-11 Nov. 2004
Firstpage
452
Lastpage
458
Abstract
The problem of retiming over a netlist of macro-blocks to achieve the minimal clock period, where the block internal structures may not be changed and flip-flops may not be inserted on some wire segments, is called the optimal wire retiming problem. To the best of our knowledge, there is no polynomial-time approach to solve it and the existence of such an approach is still an open question. We present a brand new algorithm that solves the optimal wire retiming problem with polynomial-time worst case complexity. Since the new algorithm avoids binary search and is essentially incremental, it has the potential of being combined with other optimization techniques. Experimental results show that the new algorithm is very efficient in practice.
Keywords
circuit complexity; circuit optimisation; integrated circuit interconnections; logic design; binary search; flip-flops; minimal clock period; optimal wire retiming; polynomial-time worst case complexity; Clocks; Delay; Flip-flops; Frequency; Integrated circuit interconnections; Pins; Polynomials; System-on-a-chip; Timing; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on
ISSN
1092-3152
Print_ISBN
0-7803-8702-3
Type
conf
DOI
10.1109/ICCAD.2004.1382619
Filename
1382619
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