The implementation of an “in-scribe” product test strategy to optimize a manufacturing “constraint” and improve yield (metric) performance

Author

MacAfee, G.H. ; Brim, Steve ; Matthews, Greg

Author_Institution

Harris Semicond., Findlay, OH, USA

fYear

1998

fDate

19-21 Oct 1998

Firstpage

128

Lastpage

130

Abstract

The transition from “drop-in” test modules to in-scribe parametric test structures has produced a variety of yield and cost benefits at Harris Semiconductor´s high volume wafer fabrication facility in Findlay, Ohio. This paper focuses on and provides data to support the “scribeline” parametric test strategy

Keywords

constraint theory; integrated circuit design; integrated circuit reliability; integrated circuit testing; integrated circuit yield; optimisation; cost benefits; drop-in test modules; in-scribe parametric test structures; in-scribe product test strategy; manufacturing constraint optimization; scribeline parametric test strategy; volume wafer fabrication facility; yield benefits; yield metric performance; yield performance; Artificial intelligence; Biographies; Constraint optimization; Costs; Electronic equipment testing; Fabrication; Manufacturing; Pipelines; Probes; Semiconductor device manufacture; Semiconductor device testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronics Manufacturing Technology Symposium, 1998. Twenty-Third IEEE/CPMT

Conference_Location

Austin, TX

ISSN

1089-8190

Print_ISBN

0-7803-4523-1

Type

conf

DOI

10.1109/IEMT.1998.731058

Filename

731058