Effect of thermal annealing on TSV Cu protrusion and local stress

Through silicon vias (TSVs) are regarded as one of the key enabling component to achieve three-dimensional (3D) integrated circuit (IC) functionality. In this paper, we present the investigation on TSV protrusion and stress at different annealing conditions tested by means of optical profiler and high efficiency micro-Raman microscopy. Finite element method is utilized to model and simulate the thermo-mechanical behavior of the TSV having a diameter of 20 μm and a depth of 120 μm under different annealing temperatures. The measured protrusion increases with annealing temperature below 400°C, and then decreases when being further annealed. The maximum measured silicon stress as a function of annealing temperature has shown similar trend to the protrusion. The pre-annealing has limited effect on protrusion, but is helpful to reduce the silicon stress.