DocumentCode
2352312
Title
An analytic placer for mixed-size placement and timing-driven placement
Author
Kahng, Andrew B. ; Wang, Qinke
Author_Institution
Dept. of Comput. Sci. & Eng., California Univ., La Jolla, CA, USA
fYear
2004
fDate
7-11 Nov. 2004
Firstpage
565
Lastpage
572
Abstract
We extend the APlace wirelength-driven standard-cell analytic placement framework of A.A. Kennings and I.L. Markov (2002) to address timing-driven and mixed-size ("boulders and dust") placement. Compared with timing-driven industry tools, evaluated by commercial detailed routing and STA, we achieve an average of 8.4% reduction in cycle time and 7.5% reduction in wirelength for a set of six industry testcases. For mixed-size placement, we achieve an average of 4% wirelength reduction on ISPD02 mixed-size placement benchmarks compared to results of the leading-edge solver, Feng Shui (v2.4) (Khatkhate et al., 2004). We are currently evaluating our placer on industry testcases that combine the challenges of timing constraints, large instance sizes, and embedded blocks (both fixed and unfixed).
Keywords
VLSI; integrated circuit interconnections; integrated circuit layout; APlace wirelength-driven standard-cell analytic placement framework; Feng Shui v2.4; analytic placer; embedded blocks; mixed-size placement; timing constraints; timing-driven placement; Benchmark testing; Computer science; Integrated circuit interconnections; Productivity; Routing; Smoothing methods; Timing; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Aided Design, 2004. ICCAD-2004. IEEE/ACM International Conference on
ISSN
1092-3152
Print_ISBN
0-7803-8702-3
Type
conf
DOI
10.1109/ICCAD.2004.1382641
Filename
1382641
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