Simulation of real time scheduling at design levels

Real time systems (RTS) development adds-at least-two complexity factors to the traditional development tasks: time and resource constraints, and differences between development and final architecture. They make the development cycle longer. The paper presents one use of the well known formalism called High Level Time Petri nets (HLTPN) applied to the design of RTS in the form of subnets that can be easily attached to any functional specification given in Petri net terms, in order to include timing and resource allocation information early on in the development. Thus, creating a model of timing and resources available at the final architecture; it is feasible to validate them before generating the implementation code, and to obtain results about timing, scheduling and resource allocation at a previous stage in the development cycle. The results of the timing validation can be applied to the implementation code, or more cycle design/evaluations can be performed until a satisfactory alternative is found. The contribution of the paper can be included in the design level for RTS, although the solution is general enough to be applied to more specific fields, like embedded systems, hardware/software codesign, etc