Through Silicon Capacitor co-integrated with TSV as an efficient 3D decoupling capacitor solution for power management on silicon interposer

First part of this paper discusses decoupling method limitation within the Power Delivery Network of a classical circuit and challenges introduced by 3D integrated circuit in term of power management. Solutions are exposed, such as integration of decoupling capacitor on silicon interposer. Second part of the paper focuses on the Through Silicon Capacitor (or TSC) as an alternative decoupling solution co-integrated with Through Silicon Vias on silicon interposer. TSC realization is described and architectural benefits of adding a partial copper-filling prior to the Metal-Insulator-Metal stack deposition are discussed. A distributed analytical model is used to quantify partial filling resistance contribution, pointing out a 6 decade decrease in ESR value of the structure. TSC process and matrix design parameters impact on capacitance density are studied. Finally, electrical performances of TSC modules are evaluated showing a low intrinsic impedance behavior granted by TSC parallel structure.