Predicting real-time behaviour for data flow computations

We present work that deals with the problem of mapping data flow graphs onto multiprocessor systems with regular or irregular topologies in such a way that the following goals are achieved (in order of priority): deterministic latency and throughput, maximum throughput, and minimum latency. A practical method which takes resource contention into account is being developed for achieving these goals. In parallel with the development of the method, a multiprocessor architecture model is defined onto which these mappings can be made. A preliminary version of the mapping method has been implemented and shown to be working through simulated execution of some simple application examples