Assembly and packaging of non-bumped 3D chip stacks on bumped substrates

Author

Bing Dang ; Maria, Joana ; Qianwen Chen ; Jae-Woong Nah ; Andry, Paul ; Tsang, Cornelia ; Sakuma, Keita ; Tyberg, Christy ; Robertazzi, Raphael ; Scheuermann, Michael ; Gaynes, Michael ; Knickerbocker, J.

Author_Institution

IBM T.J. Watson Res. Center, Yorktown Heights, NY, USA

fYear

2014

fDate

27-30 May 2014

Firstpage

1372

Lastpage

1377

Abstract

In this paper, a novel assembly and packaging approach is proposed for 3D/2.5D chip stacks based on bumped substrates. The thinned chips are stacked using thermal compression bonding with “flat” metallization to reduce assembly complexity associated with conventional controlled-collapse-chip-connection (C4) solder bumps. Meanwhile, the laminate substrates are bumped with C4s using injected molten solder (IMS) processes. The pre-stacked chips are then assembled and packaged on the bumped laminates successfully.

Keywords

integrated circuit bonding; integrated circuit metallisation; integrated circuit packaging; laminates; solders; three-dimensional integrated circuits; 3D-2.5D chip stacks; C4 solder bumps; IMS; assembly complexity; bumped laminates; bumped substrates; controlled-collapse-chip-connection solder bumps; flat metallization; injected molten solder; laminate substrates; nonbumped 3D chip stack assembly; nonbumped 3D chip stack packaging; thermal compression bonding; thinned chips; Assembly; Films; Laminates; Resists; Substrates; Three-dimensional displays; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th

Conference_Location

Orlando, FL

Type

conf

DOI

10.1109/ECTC.2014.6897471

Filename

6897471