Sub-100 nm nMOSFETs with direct tunneling thermal, nitrous and nitric oxides

Performance and reliability of sub-100 nm gate length devices using a dual gate and shallow trench isolated CMOS technology were investigated. Ultra-thin direct tunneling (DT) thermal, nitrous and nitric oxides as thin as 1.3 nm are used. Only N-MOS device results are reported here. The ultra thin LPT gate oxides are produced by a furnace oxidation with a dilute oxygen flow. Nitrous and nitric oxides are formed respectively by N/sub 2/O and NO treatments. The sub-100 nm gate length is realized by a resist trimming technique combined with deep ultraviolet lithography. For the 90 nm gate length (CD SEM) MOSFET with 2.2 nm physical thickness (TEM) of nitrous oxide on the source/drain (S/D) area produced here, the poly profile is almost vertical and the poly gate etch has high selectivity to avoid S/D gate oxide pitting, even with oxide thickness down to 1.3 nm.