Energy-efficient architectures for timing error-tolerant processors

Architectural design decisions have traditionally been made to maximize processor efficiency during correct operation. However, due to increasing unreliability at the circuit level due to manufacturing and dynamic variations, the cost of maintaining the abstraction of flawless hardware continues to escalate. Recently, error resilience mechanisms have been proposed that allow timing errors during nominal operation and tolerate or correct the errors for an overall reduction in power and/or energy [3]. In this work, we ask whether processors should be architected differently to maximize energy efficiency given the availability of an error resilience mechanism.