Temperature characterization and modeling of electron and hole mobilities in MOS accumulation layers

The need to understand and predict MOS accumulation layer mobility has become increasingly important as MOS devices scale to the 100 nm gate length range. Indeed, the accumulation layer in the shallow source/drain extension in MOSFETs is becoming a significant part of the series resistance. Also, the accumulation layer is the major carrier transport layer in accumulation mode SOI MOSFETs and PMOS buried-channel MOSFETs. However, temperature dependent experimental data and accurate models for the accumulation layer mobility are not available. This paper reports for the first time accumulation layer mobility models for both electrons and holes. Also for the first time, we report experimental data for both electrons and holes over the important temperature range of 25-150°C for a range of doping concentrations from 1×10/sup 16/ to 4×10/sup 17/ cm/sup -3/. From the newly developed effective mobility models, compact and computationally efficient local mobility models have also been developed and implemented in the PISCES and MINIMOS 2D device simulators. Using the newly developed accumulation layer mobility models, a more accurate prediction of the device drive current has been made possible for both N-channel and P-channel deep submicron MOSFETs.