DocumentCode
2353342
Title
Construction of VHDL-AMS simulator in Matlab
Author
Zorzi, M. ; Franze, F. ; Speciale, N.
Author_Institution
Dipt. di Elettronica, Inf. e Sistemistica, Bologna Univ., Italy
fYear
2003
fDate
7-8 Oct. 2003
Firstpage
113
Lastpage
117
Abstract
We describe the digital kernel implementation of the simulator S.A.M.S.A., a tool for the simulation of VHDL-AMS systems in Matlab™. The digital kernel was validated by simulating different systems. In particular we will show the simulation of a low-power multistage decimator for a wideband Δ-Σ analog to digital converter (ADC). This example was correctly simulated given the same results as other VHDL commercial tools.
Keywords
analogue-digital conversion; circuit simulation; hardware description languages; logic CAD; mathematics computing; CAD tool; Matlab; VHDL-AMS simulator construction; behavioral modeling; circuit simulation; digital kernel implementation; low-power multistage decimator; wideband Δ-Σ ADC; Circuit simulation; Computer languages; Design automation; Engines; Kernel; Libraries; MATLAB; Mathematical model; Object oriented modeling; Wideband;
fLanguage
English
Publisher
ieee
Conference_Titel
Behavioral Modeling and Simulation, 2003. BMAS 2003. Proceedings of the 2003 International Workshop on
Print_ISBN
0-7803-8135-1
Type
conf
DOI
10.1109/BMAS.2003.1249868
Filename
1249868
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