Title :
Sub-50-nm PtSi Schottky source/drain p-MOSFETs
Author :
Wang, C. ; Snyder, J.P. ; Tucker, J.R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Illinois Univ., Urbana, IL, USA
Abstract :
A PtSi source/drain p-MOSFET fabricated to a /spl sim/40 nm channel length with 34 /spl Aring/ gate oxide yields a current drive of 325 /spl mu/A//spl mu/m at 1.75 V by gate-induced field emission. Likewise, a 27 nm-long device with 19 /spl Aring/ oxide yields 196 /spl mu/A//spl mu/m at 1.0 V. CV/I delay times extend the scaling trends of conventional p-MOSFETs to /spl sim/2 ps. On/off ratios are /spl sim/25-50 at 300 K, and, on 0.3 /spl mu/m-long devices, /spl sim/10/sup 7/ at 77 K. Room temperature on/off ratios of /spl sim/10/sup 3/ can be achieved by inserting fully-depleted dopants beneath the active region.
Keywords :
MOSFET; Schottky barriers; buried layers; dielectric thin films; doping profiles; platinum compounds; semiconductor device metallisation; semiconductor device testing; 0.3 micron; 1 V; 1.75 V; 19 angstrom; 2 ps; 20 K; 27 nm; 300 K; 34 angstrom; 40 nm; 50 nm; 77 K; CV/I delay times; PtSi; PtSi Schottky source/drain p-MOSFETs; PtSi source/drain p-MOSFET; active region; channel length; current drive; fully-depleted dopant insertion; gate oxide; gate-induced field emission; on/off ratios; p-MOSFET scaling trends; p-MOSFETs; room temperature on/off ratios; MOSFET circuits; Voltage;
Conference_Titel :
Device Research Conference Digest, 1998. 56th Annual
Conference_Location :
Charlottesville, VA, USA
Print_ISBN :
0-7803-4995-4
DOI :
10.1109/DRC.1998.731126
