Planarized copper gate hydrogenated amorphous-silicon thin-film transistors for AM-LCDs

The reduction of gate busline RC propagation delay and the enhancement of pixel electrode aperture-ratio are very critical for large-area and high-resolution active-matrix liquid crystal displays (AMLCDs). To achieve these goals, Cu gate hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) must be developed. However, Cu shows high reactivity during PECVD of certain films, poor adhesion to glass substrates, and high diffusivity through PECVD gate insulators under electrical bias. These problems must be overcome before this metallurgy can be used for a-Si:H TFTs. To overcome these problems, we propose to apply gate planarization (GP) technology to a-Si:H TFTs incorporating Cu gate metalurgy. In this paper, we show that it is possible to combine Cu metallization with a low dielectric constant organic dielectric planarization layer to fabricate a-Si:H TFT structures that can be used in AMLCDs. Benzocyclobutene (BCB, ε/sub r/=2.4) was chosen as the planarization layer for the Cu gate electrodes, since it has been successfully used in VLSI technology. In addition, by using the BCB layer, not only has Cu layer adhesion to the glass substrate been improved, but at the same time the high reactivity of the Cu surface can be controlled. The step coverage of the thick gate metal is not a problem with this technology. The low dielectric constant of this material also reduces the parasitic capacitance associated with a-Si:H TFT circuitry.