Title :
Cost effective interposer for advanced electronic packages
Author :
Kuramochi, Satoru ; Koiwa, Sumio ; Suzuki, Kenji ; Fukuoka, Yoshitaka
Author_Institution :
Dai Nippon Printing Co., Ltd., Kashiwa, Japan
Abstract :
As electronic product becomes smaller and lighter with an increasing number of function← the demand for high density and high integration becomes stronger.! Interposers for system in package will became more and more important for advanced electronic systems. Silicon interposers with through silicon vias (TSV) and back end of line (BEOL) wirring offer compelling benefits for 2.5D and 3D system integration;! however, they are limited by high cost and high electrical loss. On the other hand, glass has many properties that make it an ideal substrate for interposer substrates such as; ultra high resistivity, adjustable thermal expansion (CTE) and manufacturability with large panel size. Furthermore, glass via formation capabilities have dramatically improved over the past several months. Fully populated wafers with > 100,000 through holes (50μm diameter) are fabricated today with 300pm thick glass. This paper presents the demonstration of glass interposers with fine pitch through glass vias(TGV), ! with 6um RDL lithography. TGVs of 50μm in diameter and 200μm in pitch were formed successfully on 300μm thick alkali-free glass by Focused Electrical Discharging Method (FEDM). The TGVs were filled with solid Copper (Cu) using a void-free electroplating of optimized periodic pulse reverse(PPR) process and chemical mechanical polishing (CMP) as well as the TSVs. Highly insulating TGV with double side polymer insulation resulted in TGV with an insertion loss of less than 0.23dB at 20GHz. Excellent through via reliability was demonstrated, due to double side thick polymer insulator that buffers the stress created by CTE mismatch between glass, copper vias and copper traces, and TGV at 200μm pitch passed 1000 thermal cycles from -40Cdeg to 85Cdeg.
Keywords :
chemical mechanical polishing; electroplating; elemental semiconductors; fine-pitch technology; integrated circuit reliability; photolithography; polymer insulators; silicon; system-in-package; thermal expansion; 2.5D system integration; 3D system integration; BEOL; CMP; CTE mismatch; FEDM; PPR process; RDL lithography; Si; TGV; TSV; adjustable thermal expansion; advanced electronic packages; advanced electronic systems; back end of line wiring; chemical mechanical polishing; cost effective interposer; double side polymer insulation; double side thick polymer insulator; electronic product; fine pitch through glass vias; focused electrical discharging method; frequency 20 GHz; glass; high electrical loss; interposer substrates; large panel size; optimized periodic pulse reverse process; silicon interposers; size 300 mum; size 50 mum; size 6 mum; solid copper; system in package; temperature -40 degC to 85 degC; through silicon vias; ultra high resistivity; void-free electroplating; Arrays; Copper; Glass; Polymers; Resistance; Silicon; Substrates;
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2014 IEEE 64th
Conference_Location :
Orlando, FL
DOI :
10.1109/ECTC.2014.6897521