Title :
Efficient Don´t Care Filling for Power Reduction during Testing
Author :
Kundu, Subhadip ; Chattopadhyay, Santanu
Author_Institution :
Dept. of Electron. & Electr. Commun., Indian Inst. of Technol. Kharagpur, Kharagpur, India
Abstract :
Power consumption during test mode is much higher than in normal mode of operation. This paper addresses issue of assigning suitable values to the unspecified bits (don´t care) in the test patterns so that both static and dynamic power consumption during testing is reduced. We have used a genetic algorithm based heuristic to fill the don´t cares. Our approach produces an average percentage improvement of 31.9, 37.0, and 37.7 in dynamic power and 3.0, 7.4, and 5.3 leakage power over 0-fill, 1-fill, and MT-fill algorithms for don´t care filling, considering the test patterns having unspecified bits in ISCAS´89 benchmark suite.
Keywords :
CMOS analogue integrated circuits; automatic test pattern generation; benchmark testing; genetic algorithms; integrated circuit testing; leakage currents; low-power electronics; ATPG generated test pattern; CMOS circuit; ISCAS´89 benchmark circuit; analog design; don´t care filling; genetic algorithm; leakage current; power consumption; power reduction; Automatic test pattern generation; Circuit testing; Communications technology; Electronic equipment testing; Energy consumption; Filling; Hamming distance; Leakage current; Minimization; Probability; Don´t Care; GA; Leakage current; Switching Activity;
Conference_Titel :
Advances in Recent Technologies in Communication and Computing, 2009. ARTCom '09. International Conference on
Conference_Location :
Kottayam, Kerala
Print_ISBN :
978-1-4244-5104-3
Electronic_ISBN :
978-0-7695-3845-7
DOI :
10.1109/ARTCom.2009.141
