Title :
Latching in N-channel, high-voltage hybrid SINFET´s
Author :
Chow, T.P. ; Pattanayak, D.N. ; Baliga, B.J. ; Adler, M.S.
Author_Institution :
General Electric Corporate Research and Development
Keywords :
Conductivity; Current measurement; Doping; FETs; Insulated gate bipolar transistors; Insulation; Research and development; Temperature control; Testing; Voltage;
Conference_Titel :
Power Semiconductor Devices and ICs, 1990. ISPSD '90. Proceedings of the 2nd International Symposium on
DOI :
10.1109/ISPSD.1990.991069