Fatigue reliability model of solder interconnects for first and second-level packaging

This paper describes fatigue reliability modeling for first and second-level package interconnects, for ceramic and laminate substrates, with and without chip underfill, based on fatigue databases and FEM analysis. The objective was to achieve a generic model expressing the strain as a function of stress conditions, design, and materials parameters such that one could cut across the various package geometries and material properties with a single model. What we had to determine was a “strain transformer”, enabling one to calculate the strain experienced by the interconnect within the package structure, reflecting the effects of the thermomechanical properties and design. The variables studied are the chip size, substrate and chip thickness, underfill, temperature excursion, single and double-sided card assemblies, substrate TCE, and solder elastic moduli. It was determined that FEM analysis is not adequate to describe the fatigue mechanism without chip underfill. Fatigue life testing provided the complementary data for developing the generic model which reflects the solder stress relaxation and creep which accrues during each thermal cycle. With an underfill, the FEM strain is fully predictive of the fatigue behaviour, as the stress relaxation and creep are negligible