DocumentCode :
2354700
Title :
Performance characterization of a hardware mechanism for dynamic optimization
Author :
Fahs, Brian ; Bose, Satarupa ; Crum, Matthew ; Slechta, Brian ; Spadini, Francesco ; Tung, Tony ; Patel, Sanjay J. ; Lumetta, Steven S.
Author_Institution :
Center for Reliable & High Performance Comput., Illinois Univ., Urbana, IL, USA
fYear :
2001
fDate :
1-5 Dec. 2001
Firstpage :
16
Lastpage :
27
Abstract :
We evaluate the rePLay microarchitecture as a means for reducing application execution time by facilitating dynamic optimization. The framework contains a programmable optimization engine coupled with a hardware-based recovery mechanism. The optimization engine enables the dynamic optimizer to run concurrently with program execution. The recovery mechanism enables the optimizer to make speculative optimizations without requiring recovery code. We demonstrate that a rePLay configuration performing a small suite of simple optimizations on Alpha code attains an average of 13% reduction in execution cycles on the SPEC2000 integer benchmarks over a rePLay configuration not performing optimizations, and a 21% reduction over an aggressive standard superscalar microarchitecture.
Keywords :
parallel architectures; performance evaluation; system recovery; Alpha code; SPEC2000 integer benchmarks; application execution time; dynamic optimization; hardware mechanism; hardware-based recovery mechanism; optimization engine; performance characterization; rePLay microarchitecture; superscalar microarchitecture; Application software; Code standards; Engines; Hardware; Instruction sets; Libraries; Microarchitecture; Performance analysis; Prototypes; Solids;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microarchitecture, 2001. MICRO-34. Proceedings. 34th ACM/IEEE International Symposium on
ISSN :
1072-4451
Print_ISBN :
0-7965-1369-7
Type :
conf
DOI :
10.1109/MICRO.2001.991102
Filename :
991102
Link To Document :
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