Design and validation of a power supply noise reduction technique

In high performance microprocessors, power supply noise needs to be controlled to ensure reliable high speed bus operation. This is generally done with high quality package capacitors. These capacitors are generally lower equivalent series inductance (ESL) and lower equivalent series resistor (ESR). Contrary to the traditional approach, we will show that a small ESR is not optimal. We will present a novel approach of using an on-die resistor in series with the package capacitance to dampen the high frequency noise. We will show by validation on the 90nm technology that this technique is capable of reducing the noise by nearly 80% without adversely affecting the timings.