Power distribution analysis methodology for a multi-gigabit I/O interface

As the operating frequency of I/O circuits increases and voltage swing decreases, it becomes increasingly important to verify the power distribution network (PDN). This paper presents a methodology used to design and verify the PDN for a multi-gigabit memory interfaces. It describes the modeling of PDN components, the necessary analysis steps to assist in the design of a high-quality PDN, and the simulations to predict the impact of supply noise on the signal quality in the memory channel.