Signal integrity study of 1000 ball grid array package construction effects on DDR2 at 533MHz

Due to the performance requirements of the DDR2 memory specification, a study was initiated to determine whether or not it could be implemented in a 1000 ball grid array (BGA) with other equally demanding signaling interfaces. The goals of the study were: to determine if the DDR specification requirements could be met in a 1000 ball BGA, which package would be most cost effective, how many memory modules could be supported, and to offer recommendations for improving the package design and signaling circuit implementation. These goals were challenging due to the emphasis on cost. The cheapest packages with 1000 balls have their routing traces very close together and constrained dimensions on the power supply planes. By being built in this way, they tend to have high crosstalk and power supply noise, which would negatively impact the performance of the signaling interface. By investigating the characteristics of these packages we were able to determine they could be used within certain design constraints.