Dynamic redundancy allocation for reliable and high-performance nanocomputing

Nanoelectronic devices are considered to be the fabrics of future nanocomputing systems due to their ultra-high speed and integration density. However, the imperfect bottom-up self-assembly fabrication leads to excessive defects that emerge as a barrier for reliable computing. In addition, transient errors continue to be an issue in nanoscale integration. The massive parallelism rendered by the ultra-high integration density opens up new opportunities but also poses challenges on how to manage such massive resources for reliable and high-performance computing. In this paper, we propose a nanoarchitecture solution to address these emerging challenges. By using dynamic redundancy allocation, the massive parallelism is exploited to jointly achieve fault (defect/error) tolerance and high performance. Simulation results demonstrate the effectiveness of the proposed technique under a range of fault rates and operating conditions.